1. Field of the Invention
The present invention generally relates to central processing units and more particularly to a system for testing or diagnosing an instruction queue circuit provided in a central processing unit.
2. Description of the Related Art
In central processing units (CPUs), instructions are prefetched in advance of execution thereof in order to improve the instruction processing ability. The prefetched instructions are temporarily stored in a buffer memory called an instruction queue until they are executed. The instruction queue is employed in processors or CPUs in electronic exchanges and computers. It is necessary to test the instruction queue in order to discern whether or not the instruction queue has a fault.
FIG. 1 is a block diagram of a CPU 10. The CPU 10 comprises an instruction fetch unit 12, an instruction decoder unit 13, a microprogram control unit 14, an address calculation unit 15, an operation unit 16, a bus control unit 17, and a timing generator (TG) 18. The instruction fetch unit 12 includes an instruction queue circuit 11. A data bus DB and an address bus ADB are connected to the bus control unit 17. An internal bus BS1 connects the operation unit 16 and the bus control unit 17 to each other. An instruction bus BS2 connects the bus control unit 17 and the instruction fetch unit 12. The bus control unit 17 switches connections among the data bus DB, the address bus ADB, the internal bus BS1 and the instruction bus BS2.
FIG. 2 shows the details of the instruction fetch unit 12 shown in FIG. 1. The configuration shown in FIG. 2 comprises the instruction queue 11, a queue writing controller 24, a queue reading controller 25 and an instruction register (IR) 26. The instruction queue circuit 11 comprises four instruction queue buffers (IQ) 21-1-21-4, four multiple-bit AND gates 22-1-22-4, and an OR gate 23. The instruction queue buffers 21-1-21-4 are connected in parallel with the instruction bus BS2. An instruction transferred via the instruction bus BS2 is written in one of the registers 21-1-21-4 under the control of the queue writing controller 24, which sequentially selects the registers 21-1-21-4 one by one. The queue reading controller 25 sequentially selects the registers 21-1-21-4 one by one. The instruction read from one of the registers 21-1-21-4 is transferred to the instruction register 26 via the corresponding AND gate and the 0R gate 23, and is written therein. Then, the instruction stored in the instruction register 26 is read therefrom and applied to the instruction decoder unit 13.
The operation of the configuration shown in FIG. 2 will now be described in detail below. The queue writing controller 24 supervises the status of the instruction queue buffers 21-1-21-4 and informs the address calculation unit 15 that an idle instruction queue buffer is available. When an idle instruction queue buffer is available, the address calculation unit 15 calculates an address in an external memory (not shown) connected to the data bus DB and the address bus ADB, and sends the address to the memory. An instruction is read from the memory and transferred via the instruction bus BS2. Then, the instruction is written into an idle instruction queue buffer under the control of the queue writing controller 24.
The queue reading circuit 25 receives a request from the instruction decoder unit 13, and specifies the instruction queue buffer in which the oldest instruction is stored. The instruction is read from the specified register and is transferred to the instruction register 26 via the corresponding AND gate and the OR gate 23. Then, the instruction is read from the instruction register 26 and is applied to the instruction decoder unit 13. The instruction decoder unit 13 decodes the received instruction and controls the microprogram control unit 14.
It is required to test the instruction queue circuit 11, that is, to determine whether or not the instruction queue circuit 11 operates normally. The process for testing the instruction queue circuit 11 is carried out in the following way. An instruction is read from the external memory via the bus control unit 17 and is written into the instruction queue circuit 11. Since the instruction queue circuit 11 has the four instruction queue buffers 21-1-21-4, four instructions should be read from the external memory and written into the registers. The instructions are read from the instruction queue circuit 11 one by one and are decoded by the instruction decoder unit 13. Then, the instructions are executed by the operation unit 16 one by one. It can be seen from the above that many structural elements must be driven in order to test the instruction queue circuit 11.